The present invention relates to a programmable divide-by-N counter where the value of N may be even or odd and increased by adding stages without decreasing the speed of operation. The invention, more particularly, relates to a programmable dividing counter employing speed enhancement techniques primarily within its reset logic portion.
Divide-by-N programmable counters, also known as programmable frequency dividers, of various conventional configurations have been used to advantage in numerous applications through out the art of digital circuitry. Many of these programmed counters or frequency dividers employ specific features to provide specialized functions peculiar to their applications. One of the more commonly desired characteristics sought is high speed operation.
High-speed phase-locked loops (PLLs) affording high-frequency resolution and short lock-up time are considered to be the basic element of the frequency synthesizer tuning systems required for radio links or mobile radio according to an article entitled "A 1.2-GHz Frequency Synthesizer Using A Custom-Design Divide-by-20/21/22/23/24 GaAs Circuit" of the IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 6, December 1985 by Rocchi et al. In order to meet these objectives with conventional techniques, the division ratio in the PLL must be as low as possible which implies the use of high-speed frequency dividers. Furthermore, the use of a variable prescaler instead of a fixed frequency divider in prior art circuits enhances the frequency resolution, and the reference frequency can be increased to improve the loop noise performance.
There are also various other desirable characteristics for the foregoing applications and other applications involving the implementation of programmable dividing counters. Flexibility in changing the value of N enables such a counter to be used in a greater number and different applications. Other considerations are ease of fabrication and adaptability to variously used integrated circuitry technologies. Also, the utilization of a minimal amount of circuitry to provide the requisite operational features is advantageous in terms of both reliability and cost.
Although static binary ripple counters have been used extensively, straight forward designs employing programmable divisors are subject to a significant operational speed limitation. Typically in such arrangements during the course of normal operation, it is required that the duration of the period of a clock cycle be at least equal to the propagation delay experienced by the signal in traversing six gates serially connected together or the equivalent circuitry. Thus, the maximum operating frequency is limited to one over 6.tau.(1/6.tau.) or less, where .tau. is the average loaded gate delay time and one clock period is 6.tau.. Since individual single-clocked flip-flops are capable of toggling at a frequency of one over four .tau. (1/4.tau.), the operating frequency of ripple counters generally comprising serially connected flip-flops is reduced by one-third in order to provide a programmable divide-by-N function.